The present invention relates to the manufacture of semiconductor integrated circuits. More particularly, the invention provides a technique including a method and device for fabrication of a metal oxide semiconductor (MOS) transistor using an improved inverse-T gate structure. But it will be recognized that the invention has a wider range of applicability; it can also be applied to the manufacture of complementary metal oxide semiconductor (CMOS) devices, bipolar complementary metal oxide semiconductor (BiCMOS) devices, and others.
In the manufacture of semiconductor integrated circuits, device geometries are becoming increasingly smaller. These smaller device geometries (e.g., submicron sized) tend to cause a variety of problems during switching of the circuits. One of these problems is known as the hot electron injection phenomena. During switching, hot electrons inject into a portion of the gate electrode, which increases the amount of charge to build underlying this gate electrode portion. This increased charge often causes switching degradation. A variety of techniques have been proposed in an attempt to eliminate this problem.
One attempt is the lightly doped drain (LDD) structure 13 in a MOS transistor 10, as illustrated by FIG. 1. This LDD structure 13 reduces the electric field underlying the gate electrode region, thereby causing fewer electrons to inject into the gate electrode 14. As shown, the gate electrode is defined overlying a gate dielectric layer 16. The LDD region 13 reduces the electric field by providing a lightly doped drain region (e.g., N- impurities) 15 between the transistor channel region 17 and an adjacent source/drain region 19. The LDD region 15 is defined in a well region (e.g., P-type well) 21 formed in a semiconductor substrate 23. A two step ion implantation technique using sidewall spacers 21 defines the LDD and source/drain regions.
As device geometries become smaller, however, hot electrons become trapped in the sidewall spacers, thereby increasing the amount of charge underlying the gate electrode. As shown by the reference arrows in FIG. 1, hot electrons inject into portions of the sidewall spacers. This tends to accumulate the amount of charge (i.e., positively charged species) underlying the spacers due to the negatively charged electrons trapped in the spacers. The increased charge underlying the spacers detrimentally effects device switching.
Another technique that has been proposed to reduce the hot electron injection problem is an inverse-T transistor gate structure. In this structure, a portion of the gate electrode extends beneath the sidewall spacers, which also surrounds and insulates the gate electrode structure. This extended portion of the gate electrode beneath the sidewall spacers often improves transistor performance by providing improved gate controllability.
In this inverse-T gate structure, polysilicon has been widely used as the material for the inverse-T gates. The gates are made from a polysilicon film, which is defined overlying a gate oxide layer. Unfortunately, this polysilicon film has inherent limitations. In particular, polysilicon gates have a relatively high resistance, typically at about 60 ohms/square. The high resistance of these gates become even greater as the size of these devices are scaled down, e.g., submicron sized gates. In addition, it also is difficult to suppress short channel effects when using these structures for a buried channel MOSFET.
Thus, tungsten gates using CMOS technology were proposed. Tungsten gates generally possess a lower sheet resistance. Devices having a tungsten gate often have a 30% transconductance increase and have a low subthreshold slope value, which is responsible for a large on/off ratio. Tungsten is effective as a material for CMOS transistor gates because its work function is near silicon mid-bandgaps. This provides symmetrical operation for N-type and P-type channel devices with equal threshold values.
Although tungsten seems to be a workable material for CMOS gate electrodes, it is not without limitations. In particular, tungsten forms volatile oxides with the gate oxide layer at relatively low temperatures during device operation. Also, during the transistor fabrication process, inherent damage often occurs to the gate silicon oxide, which necessitates regrowth. This typically occurs by oxidizing the silicon at temperatures of 900-1000.degree. C. in oxygen ambient for a period of time. Accordingly, tungsten gates also have limitations with these devices having submicron sized line-widths.
From the above, it is seen that a technique for forming an improved MOS gate structure, which reduces the hot electron injection problem, is often desirable.